Not applicable.
Not applicable.
1. Field of the Invention
The present invention generally relates to a computer system with a hot pluggable bus. More particularly, the invention relates to a hot pluggable bus for which a user normally alerts the computer before removing a bus adapter. Still more particularly, the invention relates to a computer system that can accommodate the removal of a bus adapter before the user alerts the system that the adapter is about to be removed.
2. Background of the Invention
A personal computer system includes a number of components with specialized functions that cooperatively interact to produce the many effects available in modem computer systems. The ability of these various components to exchange data and other signals is vital to the successful operation of a computer system. Typically, components interact by reading or writing data or instructions to other components in the system.
Early computer systems typically included a processor (or CPU), random access memory (RAM), and certain peripheral devices such as a floppy drive, a keyboard and a display. These components typically were coupled together using a network of address, data and control lines, commonly referred to as a xe2x80x9cbus.xe2x80x9d As computer technology evolved, it became common to connect additional peripheral devices to the computer through ports (such as a parallel port or a serial port), or by including the peripheral device on the main system circuit board (or xe2x80x9cmotherboardxe2x80x9d) and connecting it to the system bus.
The computer operates by having data flow through the system, with modification of the data occurring frequently. Traditionally, the CPU controlled most activities in the computer system. The CPU supervises data flow and is responsible for most of the high-level data modification in the computer. The CPU, therefore, is the xe2x80x9cbrainxe2x80x9d of the system and receives signals from the peripheral devices, reads and writes data to memory, processes data, and generates signals controlling the peripheral devices.
Despite the importance of the processor, the performance of the computer system is determined only in part by the speed and efficiency of the processor. Other factors also affect system performance. One of the most critical factors is the bus that interconnects the various system components. Computers today typically have multiple buses. The size and clock speed of a bus dictate the maximum amount of data that can be transmitted between components. Early bus systems, such as the ISA (Industry Standard Architecture) bus, required that all components communicate through the CPU. The ISA bus, as the name implies, was a bus standard adopted by computer manufacturers to permit the manufacturers of peripheral devices to design devices that would be compatible with most computer systems.
Since the introduction of the ISA bus, computer technology has continued to evolve at a relatively rapid pace. New peripheral devices have been developed, and both processor speeds and the size of memory arrays have increased dramatically. In conjunction with these advances, designers have sought to increase the ability of the system bus to transfer more data at a faster speed. One way in which the system bus has been made more effective is to permit data to be exchanged in a computer system without the assistance of the CPU. To implement this design, however, a new bus protocol had to be developed. One of the first such buses that permitted peripheral devices to run master cycles independently of the CPU was the EISA (Extended Industry Standard Architecture) bus. The EISA bus enables various system components residing on the EISA bus to obtain mastership of the bus and to run cycles on the bus.
More recently, the Peripheral Component Interconnect (PCI) bus has become increasingly popular. Like the EISA bus, the PCI bus has bus master capabilities, and thus certain master components on the PCI bus may communicate directly with other PCI components by addressing read and write commands to these other components based on protocols defined in the PCI Specification that has been developed by the industry. Because of the bus mastering capabilities and other advantages of the PCI bus, many computer manufacturers now implement the PCI bus as the main system bus in the computer system.
The PCI bus standard has also evolved to provide for xe2x80x9chot plugxe2x80x9d capability. Hot plug generally refers to being able to install or remove an expansion card from a computer while the computer is operating. PCI hot plug permits a PCI card in particular to be added to or removed from a PCI bus while the rest of the computer continues to operate. By contrast, before the advent of hot plug, a user wishing to replace an expansion card had to shut down the computer, remove the old card, install the new card, and then reboot the systemxe2x80x94time consuming and inconvenient.
With a hot plug capability of a PCI bus and with the computer fully operational, a user can simply remove the old card and install a new card and not have to shut down and then reboot the computer. In accordance with the PCI bus hot plug specification, however, the user must alert the computer""s software before removing a PCI card. This process generally entails the user notifying a hot plug service routine of the user""s desire to remove a card from a particular slot. The service routine then uses various operating system functions to xe2x80x9cquiescexe2x80x9d the software driver associated with the PCI card the user desires to remove. Quiescing means that all communications between the PCI card to be removed and the rest of the computer system are discontinued. In addition to directing the system not to initiate any new transactions to the PCI card to be removed, a reset signal is also asserted to the PCI device to prevent it from attempting to communicate with the rest of the system. The hot plug service routine then causes power to the slot to be turned off. At this point, the user can remove the PCI device.
These steps are generally reversed to add a card to a hot plug PCI bus. The user first installs the card in a vacant PCI slot and then notifies the hot plug service routine that a new card is present and should be turned on. The system responds by powering on the slot and permitting communications to occur to or from the newly installed PCI card.
Of particular note in the PCI hot plug implementation is that the user must notify the software when a card is being removed. This notification should occur before the user actually removes the card, not after. Of course, there generally is no physical impediment to prevent a user from removing a PCI card before alerting the software. Consequently, however, if a user was to remove a PCI card from a PCI hot plug capable bus with the computer""s processor not being aware that the target PCI card is missing, the processor may improperly attempt to communicate with the missing card. In this case an error will occur. The attempted communication to the slot, now vacant, will not complete because no PCI card is present to respond to the attempted transaction. The logic that initiates the transaction will eventually time out (also referred to as a xe2x80x9cmaster abortxe2x80x9d event) when it determines that the target PCI device has not responded. By convention, if the attempted transaction is a read (e.g., the processor attempting to read a register on a PCI device), all logic Is will be returned to the processor as the requested data. Receiving all Is, the processor may process that data not realizing that the data is incorrect, thereby creating an error in system behavior.
One suggested solution to the problem of a user removing a PCI card without first alerting software is to use a PCI bus system error (SERR) signal in response to a master abort event. The logic that times out upon failing to detect the presence of the target PCI card asserts the SERR signal which causes the entire system to shut down. Although shutting down the entire system may seem drastic, that usually is preferred over the system continuing to operate but receiving and processing incorrect data. Although generally satisfactory, this approach itself creates a problem.
In certain situations, it may be normal and, in fact, desired for the processor to attempt a transaction to a vacant PCI slot. For example, during the boot up process, the processor may initiate an enumeration sequence during which communications to each of the PCI slots, vacant or not, are attempted to determine what, if any, PCI devices are present in the system. As such, if a device is present in a slot, it will respond and the system will then know that a device occupies that slot. However, if no response is received from a slot, the computer will determine that the slot is vacant and configure itself to avoid any further communications to that slot. This is the general manner in which the system determines what hardware is present on the PCI bus.
During this enumeration process, it obviously would be inappropriate for the system to respond to an attempted communication with a vacant PCI slot by asserting the SERR signal and causing the system to shut down, which would be the result with the master abort/SERR solution. Because of certain situations in which communications to a vacant slot are intended and normal, the master abort/SERR solution to the problem of a user removing a PCI card before alerting software is generally unworkable.
It would be desirable if a system was available that can solve the problem caused by a user incorrectly removing an expansion card before alerting software. Such a solution should also permit the system, during various normal situations, to attempt a communication with a vacant slot without resetting or otherwise crashing the system.
The present invention solves the deficiencies of the prior art by providing a hot pluggable bus (e.g., a PCI bus) in a computer system that includes one or more slots for receiving hot pluggable bus adapters and a hot plug controller also coupled to the bus. Further, a host bridge may be included to provide a bridge through which a processor may communicate with the bus adapters. The hot plug controller includes a control register that can be programmed to enable and disable a system error signal to the processor. Preferably, the system error signal is normally disabled.
Each slot includes a connector for receiving a mating connector on the bus adapter. Each slot also includes a mechanical or electro-mechanical member to permit a user to notify the system when the user desires to remove the bus adapter presently residing in the slot. When the mechanical member is actuated by the user, a signal is sent to the hot plug controller to indicate that the user is about to remove the bus adapter. In response, the hot plug controller programs the control register to enable the system error signal to thereafter permit the hot plug controller to assert the system error signal when desired. The hot plug controller also causes power to be turned off to the slot for which the user is about to remove the bus adapter and the hot plug controller sends a notification to the computer""s software that the bus adapter is about to be removed.
The hot plug controller then monitors the bus for a master abort cycle pertaining to an attempted transaction to the slot which has now been vacated by the user removing the bus adapter. When the hot plug controller detects such a master abort, the controller asserts the system error signal which causes the processor to halt the computer system. If, however, the hot plug controller is informed that the computer""s software has quiesced the slot and, in the interim time period, has not detected a master abort, the hot plug controller disables its system error signal.
In this manner, the system error signal is preferably only enabled during relatively short periods of time including when a bus adapter is present in a slot but is about to be removed by a user through the time that software is informed of such event and quiesces the slot. Most of the time, the system error signal is disabled, thereby not causing a conflict with normal system behavior. These and other benefits will become apparent upon reviewing the following description.